Recently, non-volatile memories that are electrically erasable and programmable semiconductor devices have been widely utilized. Flash memories are typical non-volatile memories and are equipped with a memory cell transistor having a charge storage layer, which is called floating gate or insulation layer. Data can be stored by trapping charge in the charge storage layer. Data can be erased by applying a high voltage between a control gate above the charge storage layer and the substrate. An FN tunnel current flows through a tunnel oxide film located between the charge storage layer and the substrate, so that the charge can be drawn from the charge storage layer. Erasing of data can be implemented by a small amount of current, and a number of memory cells can be simultaneously involved in erasing of data.
A 128 Mbit NOR flash memory will now be described as first related art. FIG. 1 (PRIOR ART) shows a memory cell array 18 of the NOR flash memory. The memory cell array 18 has 256 sectors. One sector 54 has 1024 bit lines BL that run in the transverse direction, and 512 word lines WL that run in the longitudinal direction. One sector 54 has memory cells equal to 512 kbits and arranged in rows and columns. One sector is the unit for simultaneous data erasing. Sector select circuits 52 are arranged close to the sectors 54, and select the sectors 54 to be subjected to data erase.
Japanese Patent Application Publication No. 2000-76116 discloses another art (second related art) in which a sector has multiple small blocks. Data stored in small blocks other than specific small blocks from which data are not erased are transferred to a storage. After the data in the sector is erased, the data stored in the storage is returned to the original address area.
The first related art requires each of the sector select circuits 52 for the respective one of the sectors 54. The flash memory of the second related art is intended to erase data quickly and requires one sector select circuit for one sector.